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| SRAM Austin Semiconductor, Inc. 128K x 8 SRAM High-Speed CMOS SRAM with 3.3V Revolutionary Pinout FEATURES * High-speed access times of 10, 12, 15 and 20 ns * High-performance, low-power CMOS process * Multiple center power and ground pins for greater noise immunity * Easy memory expansion with CE\ and OE\ options * CE\ power-down * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 3.3V power supply AS5LC1008 PIN ASSIGNMENT (Top View) 32-Pin, 400-mil Plastic SOJ (DJ) & Ceramic SOJ (DCJ) OPTIONS * Timing 10ns access 12ns access 15ns access 20ns access * Package Plastic SOJ (32-pin, 400-mil) *Ceramic SOJ (32-pin, 400-mil) * Operating Temperature Ranges -Military (-55oC to +125oC) -Industrial (-40oC to +85oC) MARKING -10 -12 -15 -20 A0 A1 A2 A3 CE\ I/O 0 I/O 1 Vcc GND I/O 2 I/O 3 WE\ A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE\ I/O 7 I/O 6 GND Vcc I/O 5 I/O 4 A12 A11 A10 A9 A8 DJ DCJ No. 906 No. 501 PIN FUNCTIONS XT IT *Consult Factory, Possible Future Offering GENERAL DESCRIPTION The ASI AS5LC1008 is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM in revolutionary pinout. The AS5LC1008 is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE\ is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250W (typical) with CMOS input levels. The AS5LC1008 operates from a single 3.3V power supply and all inputs are TTL-compatible. PIN A0 - A16 CE\ OE\ WE\ I/O0 - I/O7 VCC GND DESCRIPTION Address Inputs Chip Enable Input Output Enable Input Write Enable Input Bidirectional Ports Power Ground For more products and information please visit our web site at www.austinsemiconductor.com AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM A0 - A16 128K x 8 MEMORY ARRAY AS5LC1008 DECODER VCC GND I/O0 - I/O7 I/O DATA CIRCUIT COLUMN I/O CE\ OE\ WE\ CONTROL CIRCUIT ABSOLUTE MAXIMUM RATINGS* Terminal Voltage with Respect to GND (VTERM)...........................................................................................-0.5V to VCC + 0.5V Temperature Under Bias (TBIAS).............................................................................................................................-55C to +125C Storage Temperature (TSTG)....................................................................................................................................-65C to +150C Power Dissipation (PT)................................................................................................................................................................1.0W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE\ X H H L CE\ H L L L OE\ X H L X I/O Operation VCC Current High-Z High-Z DOUT DIN ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM Austin Semiconductor, Inc. AS5LC1008 ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V) PARAMETER Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage 1 SYMBOL VOH VOL VIH VIL ILI ILO CONDITIONS VCC = Min., IOH = -4.0mA VCC = Min., IOL = 8.0mA MIN 2.4 --2.2 -0.3 MAX --0.4 VCC + 0.3 0.8 5 5 UNITS V V V V A A GND < VIN < VCC GND < VOUT < VCC; Outputs Disabled -5 -5 NOTE: 1. VIL = -3.0V for pulse width less than 10ns. POWER SUPPLY CHARACTERISTICS1 (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V) PARAMETER VCC Dynamic Operating Supply Current SYM ICC CONDITIONS VCC = Max, CE\ = VIL, IOUT = 0 mA, f = Max VCC = Max, VIN = VIH or VIL CE\ > VIH, f = Max VCC = Max, VIN = VIH or VIL CE\ > VIH, f = 0 VIN > VCC - 0.2V, or VIN < 0.2V, f = 0 -10 -12 -20 -15 MIN MAX MIN MAX MIN MAX MIN MAX UNIT --160 --140 --130 --120 mA ISB TTL Standby Current (TTL Inputs) ISB1 --- 45 --- 40 --- 35 --- 30 mA --- 30 --- 30 --- 30 --- 30 mA CMOS Standby Current (CMOS Inputs) ISB2 --- 10 --- 10 --- 10 --- 10 mA NOTE: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE1,2 PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CONDITIONS CIN CI/O VIN = 0V VOUT = 0V MAX 6 8 UNIT pF pF NOTE: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1MHz, VCC = 3.3V. AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM Austin Semiconductor, Inc. READ CYCLE SWITCHING CHARACTERISTICS1 (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V) -10 PARAMETER Read Cycle Time Address Access Time Output Hold time CE\ Access Time OE\ Access Time OE\ to Low-Z Output OE\ to High-Z Output CE\ to Low-Z Output CE\ to High-Z Output SYMBOL tRC tAA tOHA tACE tDOE 2 tLZOE 2 tHZOE 2 tLZCE 2 tHZCE AS5LC1008 -12 MAX --10 --10 5 --5 --5 MIN 12 --2 ----0 0 2 0 MAX --12 --12 6 --6 --6 MIN 15 --2 ----0 0 2 0 -15 MAX --15 --15 7 --7 --7 MIN 20 --2 ----0 0 2 0 -20 MAX --20 --20 8 --8 --8 UNIT ns ns ns ns ns ns ns ns ns MIN 10 --2 ----0 0 2 0 NOTES: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1 output loading specified in Figure 1. 2. Tested with the C2 load in Figure 1. Transition is measured 500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS PARAMETER Input Pulse Level Input Rise and Fall Times Input and Output timing and Reference Levels Output Load UNIT 0V to 3.0V 3ns 1.5V See Figures 1 and 2 AC TEST LOADS FIGURE 1 AS5LC1008 Rev. 1.0 11/02 FIGURE 2 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM Austin Semiconductor, Inc. AS5LC1008 READ CYCLE #11,2 READ CYCLE #21,3 NOTES: 1. WE\ is HIGH for a Read Cycle. 2. The device is continuously selected. OE\, CE\ = VIL. 3. Address is valid prior to or coincident with CE\ LOW transitions. AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SRAM Austin Semiconductor, Inc. WRITE CYCLE SWITCHING CHARACTERISTICS1,3 (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V) PARAMETER Write Cycle Time CE\ to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE\ Pulse Width (OE\ HIGH) WE\ Pulse Width (OE\ LOW) Data Setup to Write End Data Hold to Write End WE\ LOW to High-Z Output WE\ HIGH to Low-Z Output SYMBOL tWC tSCE tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE tLZWE 2 2 1 2 AS5LC1008 -10 MIN 10 7 8 0 0 7 10 5 0 --2 MAX ------------------5 --- -12 MIN MAX 12 8 9 0 0 8 12 6 0 --2 ------------------6 --- -15 MIN MAX 15 9 10 0 0 9 12 7 0 --2 ------------------7 --- -20 MIN MAX UNITS 20 10 12 0 0 10 15 8 0 --2 ------------------8 --ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. WRITE CYCLE #11,2 (CE\ Controlled, OE\ = HIGH or LOW) AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SRAM Austin Semiconductor, Inc. WRITE CYCLE #21 (WE\ Controlled, OE\ = HIGH during Write Cycle) AS5LC1008 WRITE CYCLE #3 (WE\ Controlled, OE\ = LOW during Write Cycle) NOTES: 1. The internal write time is defined by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE\ * VIH. AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SRAM Austin Semiconductor, Inc. AS5LC1008 MECHANICAL DEFINITION* ASI Case #906 (Package Designator DJ) SYMBOL A A1 A2 B b C D E E1 E2 e ASI SPECIFICATIONS MIN MAX 0.128 0.148 0.025 --0.082 --0.015 0.020 0.026 0.032 0.007 0.013 0.820 0.830 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC * All measurements are in inches. AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SRAM Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #501 (Package Designator DCJ) POSSIBLE FUTURE OFFERING, CONTACT FACTORY A AS5LC1008 e D D1 B1 b E2 E1 E A2 SYMBOL A A2 B1 B1 D D1 E E1 E2 e ASI SPECIFICATIONS MIN MAX 0.132 0.144 0.026 0.036 0.030 0.040 0.015 0.019 0.812 0.828 0.740 0.760 0.405 0.415 0.435 0.445 0.360 0.380 0.050 BSC *All measurements are in inches. AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 SRAM Austin Semiconductor, Inc. AS5LC1008 ORDERING INFORMATION EXAMPLE: AS5LC1008DJ-12/XT Device Number AS5LC1008 AS5LC1008 AS5LC1008 AS5LC1008 Package Type DJ DJ DJ DJ Speed ns -10 -12 -15 -20 Process /* /* /* /* EXAMPLE: AS5LC1008DCJ-10/IT Device Number AS5LC1008 AS5LC1008 AS5LC1008 AS5LC1008 Package Type DCJ DCJ DCJ DCJ Speed ns -10 -12 -15 -20 Process /* /* /* /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Military Temperature Range -40oC to +85oC -55oC to +125oC AS5LC1008 Rev. 1.0 11/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 |
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